Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data-rate 3D serial TSV links. A design space exploration is performed and trade-offs in terms of area, power and performance are presented. Circuit simulations of RC-extracted layouts in 40nm CMOS-technology reveals that 8:1 serialization efficiently balances area consumption and energy efficiency. Using 10μm-diameter TSV technology, an 8Gb/s serial link consumes only 84fJ/bit with 10X area reduction over 8b parallel bus

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated memory modules, interconnected by a 3-D network-on-chip (NoC), which can route packets in the vertical direction. Superimposing identical planar dies minimizes design effort and manufacturing costs, ensuring at the same time high flexibility and reconfigurability. A single die can be used either as a fully testable standalone chip multi-processor (CMP), or integrated in a 3-D stack, increasing the overall core count and consequently the system performance. To demonstrate the feasibility of this architecture, fully functional samples have been fabricated using a conventional UMC 90 nm complementary metal–oxide–semiconductor process and stacked using an in-house, via-last Cu-TSV process. Initial results show that the proposed 3-D-CMP is capable of operating at a target frequency of 400 MHz, supporting a vertical data bandwidth of 3.2 Gb/s

Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

A novel modular, cost e ffective 3D multi-processor architecture is presented. Auto-configurable and independently testable identical dies are stacked exploiting Through-Silicon-Vias (TSV) technology, allowing to target different market segments by selecting the appropriate number of layers. For the purpose of evaluation, dies have been fabricated using a commodity UMC 90nm CMOS process and stacked using a in-house, Via-Last copper TSV process. Each die, featuring four cores interconnected by a Network-on-Chip (NoC), has been designed for a maximum operating frequency of 400MHz resulting in 3.2Gbps data bandwidth

Impact of Data Serialization over TSVs on Routing Congestion in 3D-Stacked Multi-Core Processors

3D integration can alleviate routing congestion, reducing the wirelength and improving performances. Nevertheless, each TSV still occupies non-negligible silicon area: as the number of TSV increases, their effect on the chip routing is detrimental. The reduction in the number of 3D vias obtained with the adoption of serial vertical connections can relieve the routing congestion of the 3D system by reducing the average wirelength. In this paper we explore the impact of the serial approach on the chip routing of a 3D multi processor platform to quantify the achievable wirelength reduction for a range of TSV technologies. The comparison between the serial and the parallel multi-processor configurations shows up to 12.4% wirelength improvement for the serial solution, with serious consequences on routing delay

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

This paper presents a circuit-level design and analysis of high-data-rate 3D serial vertical links which exploit the high bandwidth provided by TSV technology. As most of the existing TSVs consume a large amount of die area, the serial configuration can save significant silicon real estate. The performance and jitter characteristic of the proposed 3D link has been accessed for different TSV technologies running worst-case simulations of RC-extracted layouts in 40 nm CMOS-technology. Results show that for a 2-layers system with an aggregate bandwidth of 80 Gbps, an 8-bit data serialization over View the MathML source10μm TSVs consumes just 0.15 pJ/bit including the clock distribution network